PIC18F4580-I/PT【PDF 17/88 页】IC PIC MCU FLASH 16KX16 44TQFP

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MCP2515

DS21801F-page 24

2010 Microchip Technology Inc.

4.3

Start-of-Frame Signal

If enabled, the Start-Of-Frame signal is generated on

the SOF pin at the beginning of each CAN message

detected on the RXCAN pin.

The RXCAN pin monitors an idle bus for a recessive-

to-dominant edge. If the dominant condition remains

until the sample point, the DSTEMP interprets this as a

SOF and a SOF pulse is generated. If the dominant

condition does not remain until the sample point, the

DSTEMP interprets this as a glitch on the bus and no

SOF signal is generated. Figure 4-1 illustrates SOF

signalling and glitch-filtering.

As with One-shot mode, one use for SOF signaling is

for TTCAN-type systems. In addition, by monitoring

both the RXCAN pin and the SOF pin, an MCU can

detect early physical bus problems by detecting small

glitches before they affect the CAN communications.

4.4

RX0BF and RX1BF Pins

In addition to the INT pin, which provides an interrupt

signal to the MCU for many different conditions, the

receive buffer full pins (RX0BF and RX1BF) can be

used to indicate that a valid message has been loaded

into RXB0 or RXB1, respectively. The pins have three

different configurations (Register 4-1):

Disabled

Buffer Full Interrupt

Digital Output

4.4.1

DISABLED

The RXBnBF pins can be disabled to the high-

impedance state by clearing BFPCTRL.BnBFE.

4.4.2

CONFIGURED AS BUFFER FULL

The RXBnBF pins can be configured to act as either

buffer full interrupt pins or as standard digital outputs.

Configuration and status of these pins is available via

the BFPCTRL register (Register 4-3). When set to

operate in Interrupt mode (by setting BFPCTRL.BxBFE

and BFPCTRL.BxBFM bits), these pins are active-low

and are mapped to the CANINTF.RXnIF bit for each

receive buffer. When this bit goes high for one of the

receive buffers (indicating that a valid message has

been loaded into the buffer), the corresponding

RXBnBF pin will go low. When the CANINTF.RXnIF bit

is cleared by the MCU, the corresponding interrupt pin

will go to the logic-high state until the next message is

loaded into the receive buffer.

FIGURE 4-1:

START-OF-FRAME SIGNALING

START-OF-FRAME BIT

Sample

Point

ID BIT

RXCAN

SOF

EXPECTED START-OF-FRAME BIT

Sample

Point

BUS IDLE

RXCAN

SOF

Expected

Normal SOF Signaling

Glitch-Filtering

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